This invention relates to digital logic gates; and more particularly, it relates to the electronic circuitry from which digital logic gates are constructed.
Since the introduction of field effect transistors in the 1960's, those transistors have played an important role in the fabrication of logic gates. One very important reason for this is that field effect transistors are extremely small in size. (e.g.,-2.5.mu.m .times.10.mu.m). Thus, thousands of logic gates can be fabricated on a single semiconductor chip to form large scale integrated circuits.
Today, much research is being performed in order to decrease the field transistors' size even further. However, the circuit configuration for NAND and NOR logic gates has remained essentially unchanged since the 60's. Those circuit configurations are illustrated, for example, in a textbook entitled "Basic Integrated Circuit Engineering", by Douglas J. Hamilton et al, 1975, at page 544.
As there illustrated, a NOR gate consists of a plurality of field effect transistors having their sources and drains coupled in parallel and another field effect transistor coupled between those drains and a power supply voltage V.sub.dd. The latter transistor has its gate tied to V.sub.dd and operates as a resistive load; whereas each transistor of the plurality receives an input logic signal on its gate and the NOR output is generated on its drain.
By comparison, a NAND logic gate consists of a plurality of field effect transistors which are serially coupled to each other and which receive respective input logic signals on their gates. They in turn connect to another field effect transistor which acts as a load resistor, and the NAND logic function is generated at that connection.
These standard field effect transistor logic gates, however, have some serious shortcomings such as a long switching time, a high speed power product, unsymmetrical noise margins, unsymmetrical rise and fall times, and a logic swing which is difficult to adjust relative to the value of the power supply voltage V.sub.dd.
To improve in some of these areas, such as switching speed, for example, complementary field effect transistor logic gates have been utilized in the prior art. These gates are illustrated at page 546 of the above reference.
However, complementary field effect transistor logic gates suffer from the fact that each logic input to the gate required two complementary transistors instead of just one transistor. Also, since those transistors are complmentary, one of them must be built in a "tub" in the substrate which is doped opposite to the substrate; and thus that transistor is very bulky. Further, the process of fabricating complementary transistors on a substrate is more complex than the process of fabricating field effect transistors of only one conductivity type.
Also in the prior art, logic gates have been fabricated with bipolar transistors in an effort to decrease the gates' switching time. One bipolar NOR gate is illustrated, for example, at page 493 of the above reference. This gate will be discussed herein in greater detail in conjunction with FIGS. 4 and 5.
In general, that bipolar NOR gate operates in a current mode, which means that the relative magnitudes of two currents in respective branches of a differential amplifier in the gate are representative of the logic function which the gate performs. And utilizing that current mode of operation, switching speeds of one nanosecond can be obtained.
One problem, however, with the bipolar current made logic gate is that it occupies too much chip area. This occurs, for example, because a bipolar transistor occupies substantially more chip area than a field effect transistor and because various biasing circuits for the differential amplifier are required in addition to the amplifier itself. Also, to obtain the one nonosecond switching speed, the current in the differential amplifier must be made relatively large which in turn makes the gate's power dissipation and speed power product undesirably high. Further, the fabricating process for bipolar transistors is substantially more complex than the fabricating process for field effect transistors.
Accordingly, it is a primary object of the invention to provide an improved field effect transistor logic gate having nanosecond switching speeds, having a small power dissipation and small speed power product, having nearly equal rise and fall times, and which is simple to fabricate.